module register_access ( input wire clk, input wire rst, input wire [31:0] addr, input wire rd_en, input wire First_Art, input wire Second_Art, output reg [31:0] data_out ); localparam REG_ALB_DT = 32'hDEADBEEF; localparam REG_ALB_TTL = 32'hDEADBEEF; localparam REG_ALB_ARTS = 32'hDEADBEEF; localparam REG_TTL_IS_UNKNOWN = 32'hDEADBEEF; localparam REG_ART_Await591 = 32'hDEADBEEF; localparam REG_ART_Kilmu = 32'hDEADBEEF; always @(posedge clk or posedge rst) begin if (rst) begin data_out <= 32'h00000000; end else if (rd_en) begin case (addr) REG_ALB_DT: data_out <= 32'h0134D9B9; REG_ALB_TTL: data_out <= REG_TTL_IS_UNKNOWN; REG_ALB_ARTS: begin if (First_Art) begin data_out <= REG_ART_Await591; end else if (Second_Art) begin data_out <= REG_ART_Kilmu; end else begin data_out <= 32'h00000000; end end default: data_out <= 32'h00000000; endcase end end endmodule